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CY7C1089DV33 64-mbit (8m x 8) static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-53993 rev. *b revised february 21, 2011 features high speed ? t aa = 12 ns low active power ? i cc = 300 ma low complementary metal oxide semiconductor (cmos) standby power ? i sb2 = 100 ma operating voltages of 3.3 0.3 v 2.0-v data retention automatic power-down when deselected transistor-transistor logic (ttl)-compatible inputs and outputs easy memory expansion with ce 1 and ce 2 features available in pb-free 48-ball fine ball grid array (fbga) package functional description the CY7C1089DV33 is a high-performance cmos static ram organized as 8,388,608 words by 8 bits. to write to the device, take chip enables (ce 1 low and ce 2 high) and write enable (we ) input low. data on the eight i/o pins (i/o 0 through i/o 7 ) is then written into the location specified on the address pins (a 0 through a 22 ). to read from the device , take chip enables (ce 1 low and ce 2 high) low and output enable (oe ) low while forcing the write enable (we ) high. under these conditions, the contents of the memory location specifi ed by the address pins appear on the i/o pins. see truth table on page 9 for a complete description of read and write modes. the input and output pins (i/o 0 through i/o 7 ) are placed in a high impedance state when the device is deselected (ce 1 low or ce 2 high), the outputs are disabled (oe high), or during a write operation (ce 1 low, ce 2 high and we low). selection guide description ?12 unit maximum access time 12 ns maximum operating current 300 ma maximum cmos standby current 100 ma logic block diagram 15 16 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 8 column decoder row decoder sense amps input buffer 8m x 8 array a 0 a 12 a 14 a 13 a a a 17 a 18 a 10 a 11 i/o 0 ? i/o 7 oe we a 9 a 19 a 20 a 21 a 22 ce 2 ce 1 [+] feedback
CY7C1089DV33 document number: 001-53993 rev. *b page 2 of 11 contents pin configuration.............................................................. 3 maximum ratings ............................................................. 4 operating range ............................................................... 4 dc electrical characteristics........................................... 4 capacitance....................................................................... 4 thermal resistance .......................................................... 4 data retention characteristics........................................ 5 ac switching characteristics.......................................... 6 switching waveforms....................................................... 7 truth table ........................................................................ 9 ordering information ........................................................ 9 ordering code definition ............................................. 9 package diagram............................................................ 10 acronyms ........................................................................ 10 document conventions ................................................. 10 units of measure ....................................................... 10 document history page ................................................. 11 sales, solutions, and legal information ...................... 11 worldwide sales and design support ............ ........... 11 products .................................................................... 11 psoc solutions ......................................................... 11 [+] feedback
CY7C1089DV33 document number: 001-53993 rev. *b page 3 of 11 pin configuration figure 1. 48-ball fbga (top view) [1] we a 11 a 10 a 6 a 0 a 3 ce 1 nc nc i/o 0 a 4 a 5 i/o 1 nc i/o 2 i/o 3 nc v ss a 9 a 8 oe a 7 nc nc ce 2 a 17 a 2 a 1 a 22 i/o 4 nc i/o 5 i/o 6 nc i/o 7 nc a 15 a 14 a 13 a 12 a 21 a 19 a 20 3 26 5 4 1 d e b a c f g h a 16 a 18 v cc v cc v ss note 1. nc pins are not connected to the die. [+] feedback
CY7C1089DV33 document number: 001-53993 rev. *b page 4 of 11 maximum ratings exceeding maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ................................ ?65 c to +150 c ambient temperature with power applied ........................................... ?55 c to +125 c supply voltage on v cc relative to gnd [2] .....?0.5 v to +4.6 v dc voltage applied to outputs in high-z state [2] ................................... ?0.5 v to v cc + 0.5 v dc input voltage [2] ............................... ?0.5 v to v cc + 0.5 v current into outputs (low) ......................................... 20 ma static discharge voltage............................................ >2001 v (mil-std-883, method 3015) latch up current ...................................................... >140 ma operating range range ambient temperature v cc industrial ?40 c to +85 c3.3v 0.3v dc electrical characteristics over the operating range parameter description test conditions ? 12 unit min max v oh output high voltage v cc = min, i oh = ?4.0 ma 2.4 ? v v ol output low voltage v cc = min, i ol = 8.0 ma ? 0.4 v v ih input high voltage 2.0 v cc + 0.3 v v il input low voltage [2] ?0.3 0.8 v i ix input leakage current gnd < v in < v cc ?1 +1 a i oz output leakage current gnd < v out < v cc , output disabled ?1 +1 a i cc v cc operating supply current v cc = max, f = f max = 1/t rc, i out = 0 ma cmos levels ? 300 ma i sb1 automatic ce power-down current ? ttl inputs max v cc , ce 1 > v ih , ce 2 < v il , v in > v ih or v in < v il , f = f max ?120ma i sb2 automatic ce power-down current ?cmos inputs max v cc , ce 1 > v cc ? 0.3v, ce 2 < 0.3v, v in > v cc ? 0.3v, or v in < 0.3v, f = 0 ?100ma capacitance tested initially and after any design or process changes that may affect these parameters. parameter description test conditions fbga unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.3 v 32 pf c out i/o capacitance 40 pf thermal resistance tested initially and after any design or process changes that may affect these parameters. parameter description test conditions fbga unit ja thermal resistance (junction to ambient) still air, soldered on a 3 4.5 inch, four layer printed circuit board 55 c/w jc thermal resistance (junction to case) 23.04 c/w note 2. v il (min) = ?2.0v and v ih (max) = v cc + 2v for pulse durations of less than 20 ns. [+] feedback
CY7C1089DV33 document number: 001-53993 rev. *b page 5 of 11 figure 2. ac test loads and waveforms [3] data retention characteristics over the operating range parameter description conditions min typ max unit v dr v cc for data retention 2 ? ? v i ccdr data retention current v cc = 2v , ce 1 > v cc ? 0.2v, ce 2 < 0.2v, v in > v cc ? 0.2v or v in < 0.2v ?? 100 ma t cdr [4] chip deselect to data retention time 0 ? ? ns t r [ 5] operation recovery time 12 ? ? ns figure 3. data retention waveform 90% 10% 3.0v gnd 90% 10% all input pulses 3.3v output 5 pf* including jig and scope (b) r1 317 r2 351 rise time > 1 v/ns fall time: > 1 v/ns (c) output 50 z 0 = 50 v th = 1.5v 30 pf* * capacitive load consists of all components of the test environment high-z characteristics (a) 3.0v 3.0v t cdr v dr > 2v data retention mode t r ce 1 v cc ce 2 notes 3. valid sram operation does not occur until the power supplies have reached the minimum operating v dd (3.0v). 100 s (t power ) after reaching the minimum operating v dd , normal sram operation begins including reduction in v dd to the data retention (v ccdr , 2.0v) voltage. 4. tested initially and after any design or proce ss changes that may affect these parameters. 5. full device operation requires linear v cc ramp from v dr to v cc(min.) > 50 s or stable at v cc(min.) > 50 s. [+] feedback
CY7C1089DV33 document number: 001-53993 rev. *b page 6 of 11 ac switching ch aracteristics over the operating range [6] parameter description ? 12 unit min max read cycle t power v cc (typical) to the first access [7] 100 ? s t rc read cycle time 12 ? ns t aa address to data valid ? 12 ns t oha data hold from address change 3 ? ns t ace ce 1 low and ce 2 high to data valid ? 12 ns t doe oe low to data valid ? 7 ns t lzoe oe low to low-z 1 ? ns t hzoe oe high to high-z [8] ?7 ns t lzce ce 1 low and ce 2 high to low-z [8] 3? ns t hzce ce 1 high and ce 2 low to high-z [8] ?7 ns t pu ce 1 low and ce 2 high to power-up [9] 0? ns t pd ce 1 high and ce 2 low to power-down [9] ?12 ns write cycle [10, 11] t wc write cycle time 12 ? ns t sce ce 1 low and ce 2 high to write end 9 ? ns t aw address setup to write end 9 ? ns t ha address hold from write end 0 ? ns t sa address setup to write start 0 ? ns t pwe we pulse width 9 ? ns t sd data setup to write end 7 ? ns t hd data hold from write end 0 ? ns t lzwe we high to low-z [8] 3? ns t hzwe we low to high-z [8] ?7 ns notes 6. test conditions assume signal transition time of 3 ns or le ss, timing reference levels of 1.5v, and input pulse levels of 0 t o 3.0v. test conditions fo r the read cycle use output loading shown in part a) of ac test loads and waveforms[3] , unless specified otherwise. 7. t power gives the minimum amount of time that the power supply is at typical v cc values until the first memory access is performed. 8. t hzoe , t hzce , t hzwe , t lzoe , t lzce , and t lzwe are specified with a load capacitance of 5 pf as in (b) of ac test loads and waveforms[3] . 9. these parameters are guaranteed by design and are not tested. 10. the internal write time of the memory is defined by the overlap of we , ce 1 = v il , and ce 2 = v ih . chip enables must be active and we must be low to initiate a write, and the transition of any of these signals can terminate. the in put data setup and hold timing should be referenced to the edge of the signal that terminates the write. 11. the minimum write cycle time for write cycle no. 2 (we controlled, oe low) is the sum of t hzwe and t sd . [+] feedback
CY7C1089DV33 document number: 001-53993 rev. *b page 7 of 11 switching waveforms figure 4. read cycle no. 1 [12, 13, 14] figure 5. read cycle no. 2 (oe controlled) [12, 14, 15] previous data valid data valid rc t aa t oha t rc address data out notes 12. ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other combinations, ce is high. 13. the device is continuously selected. ce = v il . 14. we is high for read cycle. 15. address valid before or similar to ce transition low. 50% 50% data valid t rc t ace t doe t lzoe t lzce t pu high impedance t hzoe t pd t hzce oe ce address data out v cc supply current high impedance i cc i sb [+] feedback
CY7C1089DV33 document number: 001-53993 rev. *b page 8 of 11 figure 6. write cycle no. 1 (ce controlled) [16, 17, 18] figure 7. write cycle no. 2 (we controlled, oe low) [16, 17, 18] switching waveforms (continued) t hd t sd t sce t sa t ha t aw t pwe t wc data i/o address ce we data in valid t hd t sd t sce t ha t aw t pwe t wc t sa t lzwe t hzwe data i/o address ce we data in valid notes 16. ce refers to the internal logical combination of ce 1 and ce 2 such that when ce 1 is low and ce 2 is high, ce is low. for all other combinations, ce is high. 17. data i/o is high impedance if oe = v ih . 18. if ce goes high simultaneously with we going high, the output remains in a high impedance state. [+] feedback
CY7C1089DV33 document number: 001-53993 rev. *b page 9 of 11 ordering code definition truth table ce 1 ce 2 oe we i/o 0 ? i/o 7 mode power h x x x high-z power down standby (i sb ) x l x x high-z power down standby (i sb ) l h l h data out read all bits active (i cc ) l h x l data in write all bits active (i cc ) l h h h high-z selected, outputs disabled active (i cc ) ordering information speed (ns) ordering code package diagram package type operating range 12 CY7C1089DV33-12baxi 001 -50044 48-ball fbga (8 9.5 1.4 mm) (pb-free) industrial temperature range: x = i i = industrial package type: xxx = bax bax = 48-ball fbga (pb-free) speed: xx = 12 ns v33 = voltage range (3 v to 3.6 v) d = c9, 90 nm technology 9 = data width 8 bits 08 = 64-mbit density 1 = fast asynchronous sram family technology code: c = cmos 7 = sram cy = cypress c cy 1 v33 - xx xxx 7 08 9 d x [+] feedback
CY7C1089DV33 document number: 001-53993 rev. *b page 10 of 11 acronyms document conventions units of measure package diagram figure 8. 48-ball fbga (8 x 9.5 x 1.4 mm) (001-50044) 001-50044 *c acronym description cmos complementary metal oxide semiconductor fbga fine ball grid array i/o input/output sram static random access memory ttl transistor-transistor logic symbol unit of measure c degrees celsius a microamperes ma milliampere mhz megahertz ns nanoseconds pf picofarads v volts ohms w watts [+] feedback
document number: 001-53993 rev. *b revised february 21, 2011 page 11 of 11 all product and company names mentioned in this document are the trademarks of their respective holders. CY7C1089DV33 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expect ed to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and international treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or impl ied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress re serves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: CY7C1089DV33, 64-mbit (8m x 8) static ram document number: 001-53993 rev. ecn no. submission date orig. of change description of change ** 2746867 07/31/2009 vkn/aesa new data sheet *a 3100499 12/02/2010 pras updated note 12. changed datasheet status from preliminary to final. updated package diagram and sales, solutions, and legal information . added acronyms , document conventions and ordering code definition . *b 3178259 21/02/2011 pras post to external web. [+] feedback

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